A Streaming Supercomputer

We are in an era where computational building blocks are plentiful and inexpensive. A single chip today can hold over 100 1GHz °oating-point units for a total performance of 100 GFLOPS/chip. Many graphics chips achieve 80GFLOPS and over 1TOP rendering performance, and cost less than $100. Embedded processors are less powerful, but incredibly cheap. It is fair to say that a raw GFLOPS costs less than $1. Memory is currently selling for less than 20 cents a MByte. Bandwidth has become less expensive as well. Chips with a Tb/s of aggregate bandwidth have recently been demonstrated. In this era of plenty, however, we have not developed technology to cost e®ectively scale computing. Supercomputers cost signi ̄cantly more per GFLOPS and GByte than their low-end counterparts. For example, it is estimated that total cost of future large-scale ASCI machines with 10's of thousands of nodes is greater than $1,000 per GFLOPS. This factor of a 1000:1 in cost e®ectiveness is paradoxical: it should be possible to reap economies of scale with computing, just as in other major acquisitions. Although scalability has long been a focus of computer science research, it has not been transferred into practical commercial systems. Now more than ever we need to build the technological infrastructure to cost-e®ectively scale computation. In addition to being cost ine±cient, contemporary high-end computers, constructed from clusters of workstations or servers, do not deliver their promised performance. They achieve a small fraction of peak performance on many key applications that are dominated by global communication. Critical calculations, such as verifying nuclear weapons, performing signal intelligence, calculating the dynamics of protein folding, and °uid °ow through complex turbomachinary, do not map well to these machines. The performance of the microprocessors from which these clusters are composed is no longer scaling at the historic rate of 50% per year. Microprocessors have reached a point of diminishing returns in terms of gates per clock and clocks per instruction. As we enter an era of billion transistor chips, there is not enough explicit parallelism in conventional programs to e±ciently use these resources. For example, a modern graphics processor has at least 64 °oating point ALUS and 1000's of integer ALUs, almost a hundred times the arithmetic density of a microprocessor. In contrast, most of the chip area in a microprocessor is devoted to cache memory or the support infrastructure (e.g. supporting out-oforder execution) to keep a few ALUS running at their peak clock rate. It is expected that without new innovations in parallel processor designs, microprocessor performance will only increase with the increase in gate speed, at a rate of about 20% per year. Such as change would have a major e®ect on the computer business, and the entire economy. Cluster supercomputers, like the microprocessors they are constructed from, are ine±cient because they are poorly matched to the technology from which they are constructed and the applications which they run. They are unable to e±ciently exploit the large numbers of °oating-point units that can be fabricated on a chip. They also have low global bandwidth and have register and cache architectures that do not capture large amounts of application locality and hence make excessive demands on this bandwidth. Because these systems are not well-designed, they are di±cult to program. Programmers spend all their time working around the limitations of the machine, rather than on developing e±cient algorithms for their application.